Si5351 "XA" can be driven by a clock signal (25/27 MHz, 1Vpp)
source: [2] p23, figure 14
Internet commenters report success driving it with a much wider frequency range
as well as successfully exceeding the specified PLL range. Inputs from 3MHz to
146MHz and PLL frequencies from 168 to 1168MHz were tested.
source: [1]
intermediate PLL frequency:
600 to 900 MHz [3] p2
divider range 15 + 0/1048575 .. 90
"integer divide" FBA_INT flag is for _EVEN_ integers [3] p4
multisynth:
valid dividiers are 4, 6, 8, 8 + 1/1048575 ... 2048
"integer divide" FBA_INT flag is for _EVEN_ integers [3] p6
[1]: http://www.simonsdialogs.com/2018/11/si5351a-any-frequency-cmos-clock-generator-and-vco-specifications-myths-and-truth/
[2]: https://www.silabs.com/documents/public/data-sheets/Si5351-B.pdf (rev 1.3)
[3]: https://www.silabs.com/documents/public/application-notes/AN619.pdf Manually Generating an Si5351 Register Map rev 0.8
Entry first conceived on 18 August 2020, 1:55 UTC, last modified on 7 September 2020, 15:19 UTC
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